Method for minimizing program disturb in a memory cell

ABSTRACT

A method of applying voltages to a memory cell, such as a P-channel EEPROM cell, and in particular to applying voltages to the cell during an erase operation of the cell is described. The method recognizes that during an erase, memory cells sharing deselected word lines are susceptible to a type of program disturb which is subtle and gradually causes corruption and loss of data over many programming cycles. The method of the present invention applies a voltage to deselected word lines, which is lower in magnitude than a programming voltage. This reduces the rate at which program disturb occurs, markedly increasing the number of programming cycles to which the deselected cells may be subjected before becoming susceptible to loss of data. The endurance of the memory array is thus significantly extended.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to an improved method for erasingand writing information in an electrically alterable memory, and moreparticularly to a method of erasing and writing information in anelectrically erasable programmable read only memory (“EEPROM”).

[0002] We have discovered a unique solution to the “program disturb”problem in memory cells such as those in current P-channel EEPROMstructures. Program disturb occurs when there is a write or erase to aselected group of cells in an aray, and the state or content of other,non-selected cells, which is supposed to be left unchanged, isunintentionally changed. The program disturb of such other, non-selectedcells may not occur as a result of one programming cycle. The unwantedchange may occur incrementally and gradually over many (even millionsof) programming cycles. The program disturb problem can be quite subtleand difficult to observe, but can be severely limiting for someapplications of the cell.

[0003] We use the nomenclature for electrical operations performed uponan array of memory cells in a slightly different manner than typicallyoccurs. We use here the term “write” to refer to an operation of placingelectrons onto a floating gate. We use the term “erase” to refer to anoperation of removing electrons from a floating gate. The term “program”as used here refers to one cycle of cell programming, which includes awrite operation and an erase operation.

[0004] This invention represents an improvement upon the structure andoperation described in the following patents: U.S. Pat. No. 5,790,455,“Low Voltage Single Supply CMOS Electrically Erasable Read-Only Memory;”U.S. Pat. No. 5,986,931, “Low Voltage Single CMOS Electrically ErasableRead-Only Memory;” and in the following patent applications: U.S. patentapplication having Ser. No. 09/262,675, and entitled “IndependentlyProgrammable Memory Segments within a PMOS Electrically ErasableProgrammable Read Only Memory Array Achieved by N-well Separation andMethod Therefor,” Filed Mar. 19, 1999; and U.S. Patent Application filedconcurrently herewith, and entitled “Improved Programming Method for aMemory Cell”, both applications assigned to the same assignee as thepresent application. Based on these two patents and applications, thefollowing summarizes the overall structure of an EEPROM memory array andthe voltages applied to it during the write and erase operations.

[0005] The program disturb problem occurs because groups of cells sharea number of common connections, including: a bit line, a word line, asource line, and an N-well. However, cells need to share theseconnections in order to make the memory array compact and to reduce thenumber of signal lines routed into it. So, an understanding of thestructure and operation of a current memory array is useful forunderstanding how the disturb problem arises and how the presentinvention addresses this problem.

[0006]FIG. 1 is a circuit schematic diagram of a p-channel memory cell,which will be referred to as the PEEC cell (p-channel EEPROM Cell). FIG.2 is a schematic cross-section diagram of the PEEC cell, along thechannel of the FIG. 1 device and in a direction parallel to the bitline. By comparing FIGS. 1 and 2, a correspondence can be seen betweenthe various symbolic representations of the cell components in FIG. 1with their physical embodiment in the cross-section of FIG. 2. Forexample, the source and drain of the cell are represented by simplelines on either side of the word line in FIG. 1 and these are actuallyp-type diffusions in an n-well shared by many memory cells as depictedin FIG. 2. In fact, each source and drain diffusion is actually sharedby two adjacent cells. The “fragments” of poly 2 to the left and rightof the poly 2 word line of the cell in the center of the diagramindicate this. In FIG. 1, it can be seen that there are four terminalsto the cell: (1) the poly 2 word line that is shared by a row of cells,(2) the source that is connected to the metal source line, (3) the drainthat is connected to the metal bit line, and (4) the N-well body that isa region of n-type silicon shared by several columns of cells.Physically, the metal bit line and source line run parallel to eachother in pairs down each column of the array. Each column of cells hasone bit line and one source line.

[0007] In FIG. 2, the cross-section is along and through the bit line sothe metal line is visible in the cross-section. The metal source lineand its contact to the source p+ region is not visible in FIG. 2 becauseit is parallel to the bit line and out of the plane of the paper. FIG. 1also indicates where voltages are applied to the PEEC cell to program orread the cell information. These voltages are labeled V_(BL) (thevoltage on the bit line), V_(NW) (the voltage on the shared N-wellregion), V_(SRC) (the voltage on the source line), and V_(WL) (thevoltage on the word line).

[0008]FIG. 3 is a schematic diagram of a portion of a large memoryarray. An N-well region is depicted as a dashed line box surrounding alarge group of memory cells. In the figure, two N-wells, labeled N-well#0 and N-well #1, are shown. N-well #0 contains eight complete columnsof cells. N-well #1 would normally also contain eight columns of cells,but only 4 columns are shown due to space limitations in the figure.Eight columns are shown as being contained in one N-well because this isthe typical size of a “byte” or “word” of information. One “byte” or“word” would actually be the number of cells along the intersection ofone word line with the number of columns in one N-well. Thus, one N-wellcontains many bytes or words, corresponding to the many word lines thatcross the N-well. However, any number of columns could be contained in asingle N-well (i.e. the “byte” or “word” size could be 14, 16, 32, orany number desired for the product). Also, there could be any number ofN-well segments in the large array. Only two are shown because this issufficient for the present description.

[0009] In FIG. 3, only the top four and last two rows of cells (wordlines) are shown due to space limitations. In this figure, it is assumedthat there are n+1 word lines, numbered from 0 through n. The number ncould be only a few, or it could be hundreds or thousands. The schematicdiagram for one PEEC cell that appears in FIG. 1 can be seen repeatedmany times in the array depicted in FIG. 3. Cells in the same columnshare a bit line, a source line, and the N-well (note the three parallellines running down each column). Cells in the same row share a word line(note the single horizontal line running along each row). All cells inthe array are identified individually by the notation, M_(x,y), wherex=the row number and y=the column number.

[0010] At the bottom of each column, the last transistor is not a PEECcell, but a source select transistor, denoted by the notation Q_(x,y),where z=the N-well number and y=the column number. The source selecttransistor is, as taught in the prior art patents, used at the bottom ofeach column to separate the column source lines during the eraseoperation. Otherwise the undesirable condition of having the programminghigh voltage signal shorted to ground could occur. The source selecttransistor must be turned on to read a cell and off during the erasepart of a programming cycle. This is accomplished by the line runningleft to right which connects all of the source select transistor gates,and has the voltage label at its terminus, V_(se1). When the sourceselect transistor is turned on, it connects the voltage, V_(src), whichis connected to all the source select transistors to the source lines.The voltages applied to the N-wells are labeled, V_(NW0) and V_(NW1).The voltages applied to the word lines are labeled, V_(WL0), V_(WL1), .. . ,V_(WLn). The voltages applied to the bit lines are labeled,V_(BL0), V_(BL1), and so on. Many commercial products, such as“byte-selectable” or “full-featured” EEPROM memories, select and programonly one byte of cells at a time, leaving all other bytes in the arrayunaltered.

[0011] In the memory cells described above, the write operation placeselectrons onto the floating gate of the memory cells being written. Thiscauses a shift in the memory transistor threshold voltage to a lownegative or perhaps a positive value. The merged select transistor inthe cell prevents the overall cell threshold from becoming a positivevalue, however. The result of the write operation is that a cell becomesconductive during a subsequent read operation.

[0012]FIG. 4 is a schematic diagram corresponding to that of FIG. 3, butwith the voltages that would be applied to execute a “write” operationof the target byte of cells enclosed by the bold rectangle. Afterexecuting the “write” the cells in the target byte would be placed intothe conductive state during a subsequent read operation. All other bytesof cells in the array, termed “deselected” bytes, are intended to beleft unaltered, the electronic charge stored on their floating gatesbeing unchanged. The N-well of the byte to be written, N-well #0 in theexample shown in the figure, is set at 0V and the N-wells of all otherbytes which are deselected (unselected and not to be changed) are set atthe programming voltage, Vpp. Vpp is the “high voltage” used inprogramming operations and typically lies in the range of 12 to 20V. Theword line of the byte to be written is set at Vpp, and all unselectedbytes have their word lines set at 0V. All bit lines are set to 0V. Thesource select line has V_(se1)>=0V and the source line has V_(src)=0V.The source select transistors are all p-channel enhancement devices,meaning that they must have a gate-source voltage, V_(gs), which is morenegative than the threshold voltage, V_(tp), of the device in order fortheir channels to be on ,i.e., conduct. The voltage conditions appliedin the write 20 operation cause the source select transistors of theselected byte (Q_(0,0) through Q_(0,7)) to be nonconductive or off. Thusall of the source lines in the selected N-well (#0) are floating. Thesource select transistors in the unselected N-wells may be on or off,depending upon the exact value of V_(se1). In any case, it is notcritical whether these source select transistors are on or off andwhether the source lines are floating or connected to 0V. The resultsfor the write operation will be the same.

[0013] Since the memory cells and source select transistors in thedeselected N-wells share the signal lines running horizontally in thearray (e.g. the word lines) with the cells in the selected N-well (inFIG. 4, N-well #0), they must have their voltages set so as not to causea change in the stored charge on the deselected or unselected memorycells. The word line voltage of the byte that is being written is at Vppwith the selected N-well at 0V in order to cause electrons to tunnelthrough the thin dielectric layer between the N-well and floating gate.This requires all deselected N-wells to have Vpp applied to them toavoid also writing the cells along the same word line (e.g. cellsM_(0,8) through M_(0,11) in FIG. 4). The deselected word lines have 0Vapplied to them over the selected N-well to avoid writing the unselectedcells. For cells in the deselected N-wells that receive Vpp, these sameword lines have 0V. Thus the bit lines of the cells in the deselectedN-wells must have 0V applied to them to avoid changing the charge ontheir floating gates. An example of one such cell is M_(1,8). Its N-wellis at Vpp and its word line is at 0V, causing the cell channel to be ininversion. With the bit line of this cell set to 0V, however, theinversion layer of charge present in the cell channel under the floatinggate is also set to 0V since it is connected electrically to the bitline via the drain p-type diffused region. Thus the potential differenceapplied between the word line and inversion layer under the floatinggate is 0V, and no inadvertent programming should occur.

[0014] The erase operation removes electrons from the floating gates ofthe cells being erased, giving them a high negative threshold voltageand causing them to be in the non-conductive state when read. FIG. 5 isa schematic diagram corresponding to FIG. 3, but with voltages appliedfor an erase operation. As with FIG. 4, a target byte is enclosed in abold line rectangle. Unlike the write operation in which all cells inthe target byte are set to the same predetermined state, the eraseoperation only erases cells in the target byte that are desired to be inthe nonconductive state. The erase operation leaves the other cells inthe target byte in the conductive state. This allows impressing a “bitpattern” into the byte of cells, with some in the binary “0” state andsome in the binary “1 ” state. As noted above, a programming cycleincludes writing all of the cells to a predetermined state (e.g., aconductive state) and then selectively erasing some of the cells to anon-conductive state, leaving the others unchanged. Only cells withtheir bit lines set to Vpp in the erase operation will be erased, thosewith bit lines set to 0V will be left in the written state. In theexample shown in FIG. 5, only cells M_(0,0) and M_(0,2) will be erasedin the target byte. The target byte has its N-well set at Vpp and itsword line set at 0V. Deselected word lines are set at Vpp andV_(se1)=Vpp, so that all source select transistors are off and allsource lines are disconnected from V_(src). Comparing FIGS. 4 and 5, itcan be seen that the deselected N-wells (N-well #1) and their associatedbit lines have the same voltages applied in the erase operation as inthe write operation. The main difference these deselected cells see is areversal of the word line voltages with the word line of the target byteset to 0V instead of Vpp and the deselected word lines set to Vppinstead of 0V. The same approach to preventing unwanted erasing of thecells in these deselected N-wells as for a write operation applies tothe erase operation as well. It should be noted that all of the above isdiscussed in U.S. Pat. No. 5,986,931 (in particular, FIG. 21, table 8and text column 22 of the patent). That Patent does not disclose thevoltages applied to the deselected N-wells (for example, N-well #1 inFIG. 4) and the bit lines contained within them.

[0015] The read operation involves applying only low voltages to thearray to detect which memory cells are conductive and which arenon-conductive. The details of reading the cell are well known and notimportant for an understanding of the present invention.

SUMMARY OF THE INVENTION

[0016] It is an object of the present invention to provide a method ofoperating a memory cell to reduce the instance of program disturb.

[0017] It is another object of the present invention to provide a methodof operating a memory to reduce the instance of program disturb thatdoes not depend upon changing the size of a memory cell.

[0018] To achieve the above and other objects, the present inventionprovides a method of operating a memory including first and secondgroups of memory cells. Cells of the first group being formed in a firstsemiconductor region, including a target set of cells operativelycoupled to a first word line and to respective first bit lines, andother cells of the first group operatively coupled to respective ones ofthe first bit lines and to respective ones of the remaining word lines.Cells of the second group being formed in a second semiconductor region,including a set of cells operatively coupled to the first word line andto respective second bit lines, and other cells of the second groupoperatively coupled to respective ones of the second bit lines and torespective ones of the remaining word lines. The method comprisesapplying a first voltage to the first word line; applying a secondvoltage to the first semiconductor region; applying selected voltages tothe first bit lines; applying a fourth voltage to the secondsemiconductor region; and applying a fifth voltage to the remaining wordlines. During a first time, the first and fourth voltages aresubstantially the same, and the second and the selected voltages aresubstantially the same, and the fifth voltage is also substantially thesame as the second voltage. During a second time the second and fourthvoltages are substantially the same and different from the firstvoltage, the fifth voltage is selected from the range of the firstvoltage to the second voltage, and the selected voltages being selectedfrom the range of the first voltage and the second voltage.

[0019] To achieve the above and other objects, the present inventionfurther provides a method of erasing memory cells formed in asemiconductor region. A first group of the cells operatively coupled toa first word line and to respective first bit lines, and other cells ofthe first group operatively coupled to respective ones of the first bitlines and to respective ones of the remaining word lines. Cells of asecond group of memory cells operatively coupled to the first word lineand to respective second bit lines, and other cells of the second groupoperatively coupled to respective ones of the second bit lines and torespective ones of the remaining word lines. The method comprisesapplying a first voltage to the word line; applying a second voltage tothe semiconductor region; applying selected voltages to the first bitlines; applying a fourth voltage to the second bit lines; and applying afifth voltage to the remaining word lines. The first and second voltagesare different, the fourth and fifth voltages selected from the range ofthe first voltage to the second voltage, and the selected voltages beingselected from the second and fourth voltages.

[0020] To achieve the above and other objects, the present inventionprovides a method of providing particular voltages to a memory cell,such as an EEPROM cell, during an erase operation of a memory cell. In apreferred embodiment of the invention, a p-channel EEPROM cell iswritten and erased by Fowler-Nordheim tunneling through a thin tunneldielectric. The prior art teaches that deselected word lines during anerase operation receive a programming voltage, Vpp. Under theseconditions, the memory cells sharing the deselected word lines aresusceptible to a type of program disturb which is subtle and graduallycauses corruption and loss of data over many programming cycles. Thepresent invention recognizes this disturb mechanism and applies adeselected word line bias, V_(WLd), which is lower in magnitude thanVpp. This has the effect of reducing the rate at which the programdisturb occurs, markedly increasing the number of programming cycles towhich the deselected cells may be subjected before becoming susceptibleto loss of data. The endurance of the memory array is thus significantlyextended.

[0021] The present invention can be applied to many types of memories,and in particular those memories that store information by storingcharges in a cell transistor. As an example of an embodiment of thepresent invention, the following discusses the present invention in viewof an illustrative structure of an EEPROM.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 is a circuit schematic diagram of a p-channel memory cell.

[0023]FIG. 2 is a schematic cross-section diagram of the PEEC cell,along the channel of the FIG. 1 device and in a direction parallel tothe bit line.

[0024]FIG. 3 is schematic diagram of a portion of a large memory array.

[0025]FIG. 4 is a schematic diagram corresponding to FIG. 3, but withthe “write” voltages applied to a selected group of cells enclosed bythe bold rectangle.

[0026]FIG. 5 is a schematic diagram corresponding to FIG. 3, but withthe “erase” voltages.

[0027]FIG. 6 is a cross-sectional view of one of the cells, M_(1,8),M_(1,9), M_(1,10), or M_(1,11) in FIG. 5.

[0028]FIG. 7 is a band diagram illustrating the sequence of eventsleading up to an energetic electron arriving at the silicon-tunneldielectric interface.

[0029]FIG. 8 is a band diagram schematically illustrating the concept ofa population of electrons arriving at the silicon-tunnel dielectricinterface with a distribution of energies.

[0030]FIG. 9 is a schematic diagram corresponding to FIG. 5, but withthe application of a voltage, V_(WLd), during an erase operation.

[0031] FIGS. 10(a), 11(a), 12(a), and 13(a) are cross-sectional views ofa cell along a deselected word line similar to FIG. 6, but with thedifferent combinations of floating gate charge and V_(BL).

[0032] FIGS. 10(b), 11(b), 12(b), and 13(b) are band diagramsrespectively corresponding to FIGS. 10(a), 11(a), 12(a), and 13(a)viewed through the floating gate region of the channel and perpendicularto the surface (section A-B in the figures).

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Program disturb is the unintentional alteration of charge on thefloating gate of a cell which is not in the target byte being programmedduring the programming cycle. Program disturb can occur during the writeor erase operations and may occur incrementally, requiring manyprogramming cycles before the threshold voltage of the cell is shiftedenough to read a different binary state than originally programmed.While it is not obvious even to those experienced in the field of theinvention, program disturb can take place with the erase conditionsapplied in FIG. 5.

[0034]FIG. 5 schematically shows the voltages applied to the cells foran erase operation. An example of a cell which is affected by theprogram disturb mechanism is M_(1,8) in the figure. This cell has theN-well and word line both set to Vpp and the bit line set to 0V.

[0035]FIG. 6 is a cross-sectional view of the cell M_(1,8) shown in FIG.5, with the set of applied voltages listed above. In the figure, themetallurgical junction boundary (solid line) is shown as are the limitsof the depletion region (dashed lines) which extends into both the P+side of the junction and the N-well side of the junction. As one ofordinary skill in the art of semiconductor device physics canappreciate, the depletion region extends much further into the N-wellside of the p-n junction, than the P+ side due to the typically muchlower doping concentration in the N-well versus the P+ regions that formthe drain and source. It is assumed in the figure that the cell underexamination is in the erased charge state with a net positive charge onthe floating gate in this example. This is symbolized with the row of“+” signs on the floating gate. The actual potential of the floatinggate is a function of the net charge on it and the potentials of theN-well and word line which couple their potentials to it capacitively.If there were zero net charge on the floating gate and both the N-welland word line are at Vpp as shown in the figure, then the floating gatepotential would also be approximately at Vpp. Since there is assumed anet positive charge on the floating gate, however, the floating gatepotential is at some value greater than Vpp. For an erased cell thepotential due to charge on the floating gate would typically lie in therange of +2V to +6V. Thus, the actual potential of the floating gatewith the applied voltages shown in the figure would lie in the range ofVpp+2V to Vpp+6V. Even though the same voltage is placed on both theN-well below the floating gate and the word line surrounding it, thereis an electric field across the tunnel dielectric between the floatinggate and N-well. The direction of the electric field is such as to causeelectrons to be attracted to the N-well surface under the floating gate.However, the field is not large enough to cause the normalFowler-Nordheim tunneling of electrons across the tunnel dielectric andonto the floating gate as is used in the write operation. This lack oftunneling is true as long as the conduction electrons in the N-well haveenergies near the conduction energy band in the N-well. If a portion ofthe conduction band electron population is given sufficient energy abovethe conduction band energy level, though, some electrons may have enoughenergy to surmount the energy barrier between the conduction bands ofthe silicon N-well and the tunnel dielectric. If the tunnel dielectricwere SiO2, this barrier height would be approximately 3.2 eV. Havingsurmounted the energy barrier, these energetic or “hot” electrons arethen able to make their way through the tunnel dielectric and onto thefloating gate. They would then begin to compensate the positive chargeinitially present on the floating gate. If enough electrons surmount theenergy barrier and collect on the floating gate over time, then thecharge state of the memory cell will change, during a subsequent read,from the non-conductive erased state to the conductive written state,resulting in a loss or corruption of the stored data.

[0036] As noted above, if electrons with energy sufficiently greaterthan the silicon conduction band energy were present in the N-well nearthe floating gate, they could surmount the tunnel dielectric barrier andchange the charge on the floating gate. Attention is now focused on howthese energetic electrons could be created in the N-well. Those withordinary skill in the art of semiconductor device physics know thatthere are a number of mechanisms by which electron-hole pairs (ehp) canbe created in a reverse biased P-N junction depletion region. The mostimportant mechanisms are: (1) thermal generation, (2) impact ionization,(3) band-to-band tunneling, and (4) optical excitation. It is reasonableto eliminate optical excitation as an important mechanism for thepresent discussion because in the EEPROM products of interest in thisinvention, light is typically shielded out by the packaging materialsused to surround the chip.

[0037]FIG. 6 schematically illustrates the creation of electron-holepairs in the drain junction depletion region with the electrons andholes represented by a circle with a “−” sign and “+” sign,respectively. Electron-hole pairs may be created by any of the threemechanisms described above. In this cell, there is no channel currentflowing during either write or erase, so the energetic or “hot”electrons are not generated by impact ionization due to any kind ofchannel current, as in common flash EEPROM cells. The energeticelectrons are only those generated in the simple reverse-biased p-njunction by the mechanisms described above. Once created, the holes areswept toward the p-side of the junction and the electrons toward then-side by the electric field in the depletion region. The holes enterthe neutral region of the P+ drain junction and flow out the draincontact (arrow labeled 1). The vast majority of electrons enter theneutral region of the N-well and flow out the N-well contact (arrowlabeled 2). Some of the electrons which enter the neutral N-well regionare attracted toward the surface by the positively charged floating gateor have their momentum directed toward the surface by elastic collisionswith lattice sites or Coulombic scattering events with ionized dopantatoms (arrow labeled 3). The population of electrons that arrive at thesilicon-tunnel dielectric interface do not all have the same energy. Aselectrons generated in the depletion region gain energy due toacceleration by the electric field, they undergo scattering events thatcause them to lose some of the energy gained. Statistically, someelectrons will lose more energy than others. Thus, it can be appreciatedthat there is a distribution of energies among the electrons enteringthe neutral N-well from the depletion region with many havinginsufficient energy to surmount the barrier at the interface. There willbe some, however, that do have sufficient energy to surmount the barrierand add their charge to the floating gate (arrow labeled 4).

[0038] Referring to FIGS. 5 and 9, it will be clearly understood bythose skilled in the art that the program disturb problem can also occurin a case in which all memory cells are placed in a single semiconductorregion, such as a single N-well region. As depicted in FIGS. 5 and 9,there would be only one semiconductor region, such as N-well #0containing all cells of the memory. As an example, cells M_(0,8). . .M_(0,11) would all be in the same semiconductor region withM_(0,0)−M_(0,7), such as a common N-well. In such a case, however,program disturb only occurs during an erase operation, not during awrite operation. This is because during a write operation the only wordline set to Vpp is that for the row being written. In the eraseoperation, the word lines of all deselected (i.e., non-selected) rowsare set to Vpp. Without employing the present invention, program disturbcan occur in the cells of these rows. Applying the present invention tothese rows minimizes program disturb from occurring during an eraseoperation.

[0039]FIGS. 7 and 8 are energy band diagrams that illustrate the processof electrons gaining energy in the depletion region and surmounting theenergy barrier. FIG. 7 illustrates the sequence of events leading up toan energetic electron arriving at the silicon-tunnel dielectricinterface. First, an ehp is created in the depletion region. Theelectron is swept to the right by the electric field present in thedepletion region and gains energy. As it traverses the depletion region,it undergoes scattering events and gives up some of its energy. Iteventually reaches the edge of the depletion region and enters theneutral N-well with still some energy above the conduction band. FIG. 8is a band diagram schematically illustrating the concept of a populationof electrons arriving at the silicon-tunnel dielectric interface with adistribution of energies. The small inset graph of electron densityversus energy placed level with the N-well conduction band illustratesthe concept that there is a small “tail” in the distribution with largeenough energy to surmount the barrier. Since there is a positive chargeon the floating gate in the erased cell, it represents a potential wellon the diagram and the positive charge also lowers the barrier of thetunnel dielectric at the top which aids electrons by a small amount. Twoelectrons are shown surmounting the barrier, one that has enough energyto completely go over the top and one near the top with enough energy totunnel through the barrier aided by the electric field from the positivecharge.

[0040] Given the above mechanisms for generating a population ofenergetic electrons near the floating gate, the present invention seeksto inhibit as many of these electrons from reaching the floating gate aspossible. With V_(NW)=Vpp, this is accomplished by applying a voltage,V_(WLd), which is more negative than Vpp to the deselected word linesduring the erase operation. The practical range of V_(WLd) is fromVpp−1V to Vpp−6V (factors affecting this range are discussed below).This reduces the attractive potential of the floating gate. In somecases, in fact, the floating gate potential may be reduced sufficientlyto set up an electric field that repels electrons from the surface. Inboth cases, program disturb of the cell is reduced.

[0041]FIG. 9 is a schematic diagram corresponding to FIG. 5, but withthe application of V_(WLd) to deselected word lines instead of Vpp as inprior art structures. The bit lines of cells in the target byte whichare not to be erased are set to V_(BLd) as in the above-noted copendingU.S. Patent Application filed concurrently herewith, and entitled“Improved Programming Method for a Memory Cell, both applicationassigned to the same assignee as the present application. The bit linesof cells in the target byte to be erased are set to Vpp.

[0042] For an erase operation, there are four possible terminal voltageand floating gate potential combinations for cells sharing a deselectedword line. The four possible conditions arise because, prior to theerase operation, a particular cell along the deselected word line may bein either the erased (positive charge on the floating gate) or inwritten (negative charge on the floating gate) state. In addition, thebit lines of the cells may be receiving either V_(BL)=Vpp or V_(BL) inthe range of 0 to V_(BLd). These two bit line voltage possibilitiesexist because the bit lines of cells along the selected word line thatare to be erased have V_(BL)=Vpp, while the bit lines of cells that arenot to be erased have V_(BL)=0V (see FIG. 5), as in the prior art; orhave a small positive voltage, V_(BL)=V_(BLd,) which is in the range of2V-8V, as taught by the above-noted copending U.S. Patent Applicationfiled concurrently herewith, and entitled “Improved Programming Methodfor a Memory Cell”, both applications assigned to the same assignee asthe present application

[0043] FIGS. 10(a), 11(a), 12(a), and 13(a) are cross-sectional views ofa cell along a deselected word line similar to FIG. 6, but with thedifferent combinations of floating gate charge and V_(BL). FIGS. 10(b),11(b), 12(b), and 13(b) are band diagrams respectively corresponding toFIGS. 10(a), 11(a), 12(a), and 13(a) viewed through the floating gateregion of the channel and perpendicular to the surface (section A-B inthe figures). FIGS. 10 and 11 illustrate the case of V_(BL)=Vpp forpositive or negative floating gate charge, respectively. FIGS. 12 and 13illustrate the case of V_(BL)=V_(BLd) for positive and negative floatinggate charge, respectively.

[0044] FIGS. 10(a) and 10(b) are cross-sectional views of a cell on adeselected word line with Vpp applied to the bit line. An example ofsuch a cell would be cell M_(1,0) in FIG. 9. FIG. 10(a) shows aninversion layer in the select gate portions of the channel. This isbecause V_(WLd) is assumed to be sufficiently lower in voltage thanV_(NW)=VPP that the threshold voltage of the select gate portion of thechannel is exceeded. Since the threshold voltage of the select gate istypically in a range around −1V, this means that V_(WLd) shouldpreferably be 1V or more below Vpp. The N-well region under the floatinggate, however, may be in accumulation, depletion, or inversion,depending upon the doping concentration in the N-well underneath thefloating gate, the amount of positive charge on the floating gate, thegate coupling ratio, and V_(WLd). In FIGS. 10(a) and 10(b), it isassumed that the surface is slightly depleted.

[0045] The difference between the FIG. 10(b) band diagram and that ofFIG. 8 result from FIG. 8 being representative of the prior art withdeselected word lines at V_(WL)=Vpp, and FIG. 10(b) being representativeof an embodiment of the present invention with deselected word lines atV_(WL)=V_(WLd). The more negative potential applied to the word line inFIG. 10(b) capacitively couples to the floating gate, raising itselectron potential so as to compensate the attractive potential of thepositive charge stored. It can be readily understood by one skilled inthe art that with the N-well depleted near the surface, as in FIG.10(b), there is an energy barrier to electrons in the neutral N-well.The electric field in the tunnel dielectric is also reversed so that itinhibits electron transport across this insulating barrier. Thus, theprobability that an energetic electron injected into the N-well orcreated in the depletion region underneath the gate can surmount thetunnel dielectric and be collected on the floating gate is greatlyreduced. Even if the surface of the N-well was in accumulation insteadof depletion, the electric field in the tunnel dielectric would still bereduced compared to that in FIG. 8.

[0046] FIGS. 11(a) and 11(b) illustrate the same conditions as in FIGS.10(a) and 10(b), except that there is now negative charge stored on thefloating gate. This causes the potential of the poly 1 floating gate tobe more negative, raising its energy on the band diagram of FIG. 11(b)above that shown in FIG. 10(b). This serves to repel energetic electronsinjected into the neutral N-well or depletion region under the floatinggate even more than the case of FIG. 10(b). In FIG. 11(a), the N-wellsurface underneath the poly 1 floating gate is inverted. This isexpected since there is a negative stored charge and the word line ismore negative than the N-well. This inversion layer is connected to theP+ drain region, which is connected to the bit line that is being heldat a potential Vpp. Thus, the surface potential for holes is pinned andthe quasi-Fermi level of holes at the surface, E_(Fp), is indicated inFIG. 11(b).

[0047] FIGS. 11(a) and 11(b) show that energetic electrons injected intothe N-well are repelled even more than those in FIGS. 10(a) and 10(b),thus reducing the program disturb even more for cells in this condition.FIGS. 11 (a) and 11 (b) also indicate that there is a lower limit onV_(WLd) below which another disturb phenomena can occur. In FIG. 11 (b),there is a large electric field in the tunnel dielectric directed so asto aid removal of electrons from the floating gate. This is due to thenegative charge on the floating gate, but also to V_(WLd) being morenegative than V_(NW)=Vpp, which further increases the electric fieldacross the tunnel dielectric. This raises a possibility that electronswill be lost from the floating gate by tunneling through the tunneldielectric. The electric field required at which a large amount ofnormal Fowler-Nordheim tunneling current begins to flow is approximately1×10⁷ V/cm. This would be, for example, 10V across a 100-Angstrom-thicktunnel dielectric. If there was zero stored charge on the floating gateand the gate coupling ratio of the cell was 0.8, the potentialdifference between the surface of the N-well and the word line wouldneed to be V_(WLd)=Vpp−12.5V. If there is stored negative charge on thefloating gate, the electric field will be larger, so the potentialdifference between N-well surface and word line will need to be evenless just to maintain an electric field of 1×10⁷ V/cm. The neededreduction in potential difference depends upon the amount of storednegative charge, but typically would lie in the range of 2 to 6V. So, inthe example given, the potential difference now lies in the range ofV_(WLd)=Vpp−6.5V to Vpp−10.5V. Beyond these considerations and with manyprogramming cycles, the cells in deselected word lines will undergo manycycles of this electric field stress, which add to form a cumulativestress time. The electric field allowed across the tunnel dielectric forthis period of time must be low enough that the floating gate is notgradually discharged of electrons over the stress time. It is known tothose skilled in the art that tunnel dielectrics that have beensubjected to many programming cycles tend to exhibit increased currentleakage at low electric fields. This is due to the Stress-InducedLeakage Current (SILC) effect widely reported in the publishedliterature. Ultimately, this effect sets the upper limit on the electricfield that the tunnel dielectric can be exposed to over the stress timebefore the floating gate loses enough electrons to cause program disturbof the cell. SILC can vary widely, depending upon the processingconditions used in the technology and the nature of the programmingvoltage signals. So, SILC should be characterized for the individualtechnology to which the present invention is being applied. A practicalupper limit is V_(WLd)=Vpp−6V.

[0048]FIG. 12(a) is a cross-sectional view of a cell along a deselectedword line similar to FIG. 10(a), but with a different combination. FIG.12(b) is a band diagram corresponding to FIG. 12(a) viewed through thefloating gate region of the channel and perpendicular to the surface(section A-B in the figure). FIGS. 12(a) and 12(b) illustrate a cell ona deselected word line with V_(BLd) applied to the bit line. An exampleof such a cell would be cell M_(1,1) in FIG. 9. FIGS. 12(a) and 12(b)show the case of positive charge on the floating gate. It can be seenagain that the select gate portion of the channel is inverted. If theportion of the channel under the floating gate is depleted, then theband diagram would be the same as in FIG. 10(b) and the same discussionas for that figure would apply. If we assume that this channel region isinstead inverted, then the band diagram in FIG. 12(b) applies. Theinversion layer under the poly 1 floating gate is connected to the bitline and this is held at a potential, V_(BLd), which is in the range of2 to 8V above ground and much lower than the N-well which is held atV_(NW)=Vpp. This causes a large amount of band bending in the N-wellnear the surface with the surface quasi-Fermi level for holes, E_(Fp),pinned at V_(BLd). This band bending imposes an even larger potentialenergy barrier to electrons in the N-well than that in FIGS. 10(b) or11(b). Also, any ehp created in the surface depletion region would havethe electrons swept away from the surface to the neutral N-well by thelarge electric field in the depletion region. Thus, cells in thiscondition are even less likely to be disturbed than those in theconditions of FIGS. 10 or 11.

[0049] FIGS. 13(a) and 13(b) illustrate the same conditions as in FIGS.12(a) and 12(b), except that the charge on the floating gate isnegative. Since there is an inversion layer under the floating gatewhich is again connected to the bit line voltage, V_(BLd), thissituation has the same consequences as the conditions in FIGS. 12(a) and12(b). The negative floating gate charge simply increases the electricfield in the interpoly dielectric and decreases the electric field inthe tunnel dielectric. The interpoly dielectric is a much thickerinsulating layer than the tunnel dielectric, and if it is a good qualityinsulator, as should be used in non-volatile memory technologies, itwill be able to retain the stored electron charge.

[0050] In summary, the present invention reduces program disturb inEEPROM cells such as described in the above-noted prior art patents andpatent applications. The application of a deselected word line bias,V_(WLd), which is sufficiently below the programming voltage, Vpp,applied to the N-well acts to retard accumulation of energetic electronsgenerated in the reverse-biased source and drain p-n junctions. Thisreduces the gradual program disturb of the information stored on anerased cell, thus extending the number of programming cycles the memorycan sustain.

1. A method of operating a memory including first and second groups ofmemory cells, cells of the first group formed in a first semiconductorregion, including a target set of cells operatively coupled to a firstword line and to respective first bit lines, and other cells operativelycoupled to respective ones of the first bit lines and to respective onesof the remaining word lines, cells of the second group formed in asecond semiconductor region, including a set of cells operativelycoupled to the first word line and to respective second bit lines, andother cells operatively coupled to respective ones of the second bitlines and to respective ones of the remaining word lines, the methodcomprising: applying a first voltage to the first word line; applying asecond voltage to the first semiconductor region; applying selectedvoltages to the first bit lines; applying a fourth voltage to the secondsemiconductor region; applying a fifth voltage to the remaining wordlines; wherein during a first time, the first and fourth voltages aresubstantially the same, and the second and the selected voltages aresubstantially the same, and the fifth voltage is substantially the sameas the second voltage, and wherein during a second time the second andfourth voltages are substantially the same and different from the firstvoltage, the fifth voltage is selected from the range of the firstvoltage to the second voltage, and the selected voltages being selectedfrom the range of the first voltage and the second voltage.
 2. A methodof operating a memory according to claim 1, wherein during the firsttime, the first voltage is greater than the second voltage.
 3. A methodof operating a memory according to claim 1, wherein during the secondtime, first voltage is less than the second voltage.
 4. A method ofoperating a memory according to claim 1, wherein the first and secondtimes occur during programming of the memory.
 5. A method of operating amemory according to claim 1, further comprising: applying a sixthvoltage to the second bit lines during the first and second times,wherein the sixth voltage is selected from the range of the firstvoltage to the second voltage.
 6. A method of operating a memoryaccording to claim 5, wherein during the first time, the first voltageis greater than the second voltage.
 7. A method of operating a memoryaccording to claim 5, wherein during the second time, first voltage isless than the second voltage.
 8. A method of operating a memoryaccording to claim 5, wherein the first and second times occur duringprogramming of the memory.
 9. A method of erasing memory cells in amemory including at least first and second groups of cells, cells of thefirst group formed in a first semiconductor region, including a targetset of cells operatively coupled to a first word line and to respectivefirst bit lines, and other cells operatively coupled to respective onesof the first bit lines and to respective ones of the remaining wordlines, cells of the second group formed in a second semiconductorregion, including a set of cells operatively coupled to the first wordline and to respective second bit lines, and other cells operativelycoupled to respective ones of the second bit lines and to respectiveones of the remaining word lines, the method comprising: applying afirst voltage to the first word line; applying a second voltage to thefirst semiconductor region; applying selected voltages to the first bitlines; applying a fourth voltage to the second semiconductor region;applying a fifth voltage to the remaining word lines; wherein the secondand fourth voltages are substantially the same and different from thefirst voltage, the fifth voltage is selected from the range of the firstvoltage to the second voltage, and the selected voltages being selectedfrom the range of the first voltage to the second voltage.
 10. A methodof erasing memory cells in a memory according to claim 9, wherein thefirst voltage is less than the second voltage.
 11. A method of erasingmemory cells in a memory according to claim 10, wherein the secondvoltage is positive.
 12. A method of operating a memory according toclaim 10, further comprising: applying a sixth voltage to the second bitlines, wherein the sixth voltage is selected from the range of the firstvoltage to the second voltage.
 13. A method of erasing memory cellsformed in a semiconductor region, a first group of the cells operativelycoupled to a first word line and to respective first bit lines, andother cells of the first group operatively coupled to respective ones ofthe first bit lines and to respective ones of the remaining word lines,the method comprising: applying a first voltage to the word line;applying a second voltage to the semiconductor region; applying selectedvoltages to the first bit lines; applying a fourth voltage to theremaining word lines; wherein the first and second voltages aredifferent, the fourth voltage selected from the range of the firstvoltage to the second voltage, and the selected voltages being selectedfrom the first and second voltages.
 14. A method of erasing a firstgroup of memory cells in a memory according to claim 17, wherein thefirst voltage is less than the second voltage.
 15. A method of erasing afirst group of memory cells in a memory according to claim 18, whereinthe second voltage is positive.
 16. A method of erasing memory cells ina memory according to claim 17, further comprising: applying a fifthvoltage as one of the selected voltages to the first bit lines, whereinthe fifth voltage is selected from the range of the first voltage to thesecond voltage.